1. Field of the Invention
The present invention relates to the field of integrated circuits; more specifically, it relates to method for static timing verification of integrated circuits having voltage islands.
2. Background of the Invention
Static timing verification of integrated circuits involves an evaluation of signal propagation at two extremes, fast and slow, of circuit speed. Slow signal propagation occurs at the nexus of worst case process (as deviations in geometry and doping profiles from design), worst case operating temperature (high for complementary metal oxide semiconductor (CMOS)) and minimum allowable operating voltage of the integrated circuit. Fast signal propagation occurs at the nexus of best-case process, best case operating temperature (low for complementary metal oxide semiconductor (CMOS)) and maximum allowable operating voltage of the integrated circuit.
Static timing verification of integrated circuits that contain voltage islands present the problem of exponentially increasing numbers of static timing verification runs required as the number of voltage islands on an integrated circuit increases. To fully verify static timing the fact that any voltage island can be running at best case or worse case voltage conditions independently of all other voltage islands must be taken into account. For any given timing path, 2×2N timing runs will be required, where N is the number of voltage islands. The cost and time required for static timing verification of integrated circuit designs containing multiple voltage islands quickly increases as the number of voltage islands increases and can become prohibitive.